Computer Aided Design Tools and Algorithms for Submicron Technologies

•9 ABSTRACT (Continue on reverie if necestary and identity by Nock number) ) Advanced algorithms for twoand three-dimensional modeling of semiconductor devices have been developed, implemented on parallel computers and tested using several high performance technologies. Computational limitations for semiconductor device analysis have been extended to greater than KJ nodes and speedup factors greater than 10-fold have been realized using distributed memory (MIMD) architectures. Two classes of algorithms have been explored using parallel processing-distributed multifrontal (DMF) and Monte Carlo (MC). The DMF algorithm has been implemented and tested for 3D device analysis of MOS, bipolar and latchup examples using iterative methods for singleand two-carrier transport A windowed MC analysis of 2D hot carrier effects in Si MOS and GaAs MESFET devices has been achieved on several parallel architectures with near ideal speedup factors up to 20 processors. ~"